View ADSP-2171_1360579.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

functional block diagram rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a dsp microcomputer the adsp-217x combines the adsp-2100 base architecture (three computational units, data address generators, and a pro- gram sequencer) with two serial ports, a host interface port, a programmable timer, extensive interrupt capabilities, and on- chip program and data memory. in addition, the adsp-217x supports new instructions, which include bit manipulationsCbit set, bit clear, bit toggle, bit testC new alu constants, new multiplication instruction (x squared), biased rounding, and global interrupt masking, for increased flexibility. the adsp-217x also has a bus grant hang logic ( bgh ) feature. the adsp-217x provides 2k words (24-bit) of program ram and 2k words (16-bit) of data memory. the adsp-2172 pro- vides an additional 8k words (24-bit) of program rom. power- down circuitry is also provided to meet the low power needs of battery operated portable equipment. the adsp-217x is avail- able in 128-pin tqfp and 128-pin pqfp packages. fabricated in a high-speed, double metal, low power, cmos process, the adsp-217x operates with a 30 ns instruction cycle time. every instruction can execute in a single processor cycle. the adsp-217xs flexible architecture and comprehensive in- struction set allow the processor to perform multiple operations in parallel. in one processor cycle the adsp-217x can: generate the next program address fetch the next instruction perform one or two data moves update one or two data address pointers perform a computational operation this takes place while the processor continues to: receive and transmit data through the two serial ports receive and/or transmit data through the host interface port decrement timer features 30 ns instruction cycle time (33 mips) from 16.67 mhz crystal at 5.0 v 50 ns instruction cycle time (20 mips) from 10 mhz crystal at 3.3 v adsp-2100 family code & function compatible with new instruction set enhancements for bit manipula- tion instructions, multiplication instructions, biased rounding, and global interrupt masking bus grant hang logic 2k words of on-chip program memory ram 2k words of on-chip data memory ram 8k words of on-chip program memory rom (adsp-2172) 8- or 16-bit parallel host interface port 300 mw typical power dissipation at 5.0 v at 30 ns 70 mw typical power dissipation at 3.3 v at 50 ns powerdown mode featuring less than 0.55 mw (adsp- 2171/adsp-2172) or 0.36 mw (adsp-2173) cmos standby power dissipation with 100 cycle recovery from powerdown dual purpose program memory for both instruction and data storage independent alu, multiplier/accumulator, and barrel shifter computational units two independent data address generators powerful program sequencer provides zero overhead looping conditional instruction execution two double-buffered serial ports with companding hardware and automatic data buffering programmable 16-bit interval timer with prescaler programmable wait state generation automatic booting of internal program memory from byte-wide external memory, e.g., eprom, or through host interface port stand-alone rom execution (optional) single-cycle instruction execution single-cycle context switch multifunction instructions three edge- or level-sensitive external interrupts low power dissipation in standby mode 128-lead tqfp and 128-lead pqfp general description the ADSP-2171, adsp-2172, and adsp-2173 are single-chip microcomputers optimized for digital signal processing (dsp) and other high-speed numeric processing applications. the ADSP-2171 and adsp-2172 are designed for 5.0 v applica- tions. the adsp-2173 is designed for 3.3 v applications. the adsp-2172 also has 8k words (24-bit) of program rom. ? analog devices, inc., 1995 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 external address bus external data bus arithmetic units shifter mac alu memory serial ports sport 0 sport 1 flags data address generators dag 1 dag 2 program sequencer program memory address data memory address data memory data timer program memory data data memory 2k x 16 program rom 8k x 24 program ram 2k x 24 powerdown control logic host interface port adsp-2100 base architecture ADSP-2171/adsp-2172/adsp-2173
rev. a C2C ADSP-2171/adsp-2172/adsp-2173 development system the adsp-2100 family development software, a complete set of tools for software and hardware system development, supports the adsp-217x. the system builder provides a high-level method for defining the architecture of systems under develop- ment. the assembler has an algebraic syntax that is easy to program and debug. the linker combines object files into an executable file. the simulator provides an interactive instruction-level simulation with a reconfigurable user interface to display different portions of the hardware environment. a prom splitter generates prom programmer compatible files. the c compiler, based on the free software foundations gnu c compiler, generates adsp-217x assembly source code. the runtime library includes over 100 ansi-standard mathematical and dsp-specific functions. ez-tools, low cost, easy-to-use hardware tools, also support the adsp-217x. the adsp-217x ez-ice ? emulator aids in the hardware de- bugging of adsp-217x systems. the emulator consists of hard- ware, host computer resident software, the emulator probe, and the pin adaptor. the emulator performs a full range of emula- tion functions including stand-alone operation or operation in the target, setting up to 20 breakpoints, single-step or full-speed operation in the target, examining and altering registers and memory values, and pc upload/download functions. if you plan to use the emulator, you should consider the emulators restric- tions (differences between emulator and processor operation). the ez-lab ? evaluation board is a pc plug-in card, but it can operate in stand-alone mode. the evaluation board/system de- velopment board executes eprom-based or downloaded pro- grams. modular analog front end daughter cards with different codecs will be made available. ez-ice and ez-lab are registered trademarks of analog devices, inc. additional information this data sheet provides a general overview of adsp-217x functionality. for additional information on the architecture and instruction set of the processor, refer to the adsp-2100 family users manual . for more information about the development system and adsp-217x programmers reference information, refer to the adsp-2100 family assembler tools & simulator manual . architecture overview figure 1 is an overall block diagram of the adsp-217x. the processor contains three independent computational units: the alu, the multiplier/accumulator (mac) and the shifter. the computational units process 16-bit data directly and have provi- sions to support multiprecision computations. the alu per- forms a standard set of arithmetic and logic operations; division primitives are also supported. the mac performs single-cycle multiply, multiply/add and multiply/subtract operations with 40 bits of accumulation. the shifter performs logical and arithmetic shifts, normalization, denormalization, and derive exponent operations. the shifter can be used to efficiently implement numeric format control including multiword and block floating-point representations. the internal result (r) bus directly connects the computational units so that the output of any unit may be the input of any unit on the next cycle. a powerful program sequencer and two dedicated data address generators ensure efficient delivery of operands to these compu- tational units. the sequencer supports conditional jumps, sub- routine calls and returns in a single cycle. with internal loop counters and loop stacks, the adsp-217x executes looped code with zero overhead; no explicit jump instructions are required to maintain the loop. figure 1. adsp-217x block diagram r bus 16 hip control hip registers boot address generator bus exchange companding circuitry dma bus pma bus dmd bus pmd bus program sequencer instruction register data address generator #2 data address generator #1 14 14 input regs output regs shifter input regs output regs mac input regs output regs alu 24 16 5 16 mux 24 mux serial port 0 receive reg transmit reg control logic data sram 2k x 16 power down control logic 14 timer 2 3 11 hip data bus program rom 8k x 24 program sram 2k x 24 serial port 1 receive reg transmit reg flags external data bus external address bus 5
ADSP-2171/adsp-2172/adsp-2173 rev. a C3C two data address generators (dags) provide addresses for simultaneous dual operand fetches (from data memory and pro- gram memory). each dag maintains and updates four address pointers. whenever the pointer is used to access data (indirect addressing), it is post-modified by the value of one of four pos- sible modify registers. a length value may be associated with each pointer to implement automatic modulo addressing for circular buffers. efficient data transfer is achieved with the use of five internal buses. program memory address (pma) bus program memory data (pmd) bus data memory address (dma) bus data memory data (dmd) bus result (r) bus the two address buses (pma and dma) share a single external address bus, allowing memory to be expanded off-chip, and the two data buses (pmd and dmd) share a single external data bus. program memory can store both instructions and data, permit- ting the adsp-217x to fetch two operands in a single cycle, one from program memory and one from data memory. the adsp- 217x can fetch an operand from on-chip program memory and the next instruction in the same cycle. the memory interface supports slow memories and memory- mapped peripherals with programmable wait state generation. external devices can gain control of external buses with bus request/grant signals ( br and bg ). one execution mode (go mode) allows the adsp-217x to continue running from inter- nal memory. normal execution mode requires the processor to halt while buses are granted. in addition to the address and data bus for external memory connection, the adsp-217x has a configurable 8- or 16-bit host interface port (hip) for easy connection to a host proces- sor. the hip is made up of 16 data/address pins and 11 control pins. the hip is extremely flexible and provides a simple inter- face to a variety of host processors. for example, the motorola 68000 series, the intel 80c51 series and the analog devices adsp-2101 can be easily connected to the hip. the host pro- cessor can initialize the asdp-217xs on-chip memory through the hip. the adsp-217x can respond to eleven interrupts. there can be up to three external interrupts, configured as edge or level sensi- tive, and eight internal interrupts generated by the timer, the serial ports (sports), the hip, the powerdown circuitry, and software. there is also a master reset signal. the two serial ports provide a complete synchronous serial in- terface with optional companding in hardware and a wide vari- ety of framed or frameless data transmit and receive modes of operation. each port can generate an internal programmable serial clock or accept an external serial clock. boot circuitry provides for loading on-chip program memory automatically from byte-wide external memory. after reset, seven wait states are automatically generated. this allows, for example, a 30 ns adsp-217x to use an external 200 ns eprom as boot memory. multiple programs can be selected and loaded from the eprom with no additional hardware. the on-chip program memory can also be initialized through the hip. the adsp-217x features three general-purpose flag outputs whose states can be simultaneously changed through software. you can use these outputs to signal an event to an external device. in addition, the data input and output pins on sport1 can be alternatively configured as an input flag and an output flag. a programmable interval timer generates periodic interrupts. a 16-bit count register (tcount) is decremented every n pro- cessor cycles, where n-l is a scaling value stored in an 8-bit regis- ter (tscale). when the value of the count register reaches zero, an interrupt is generated and the count register is reloaded from a 16-bit period register (tperiod). the adsp-217x instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. every instruction can be executed in a single pro- cessor cycle. the adsp-217x assembly language uses an alge- braic syntax for ease of coding and readability. a comprehensive set of development tools supports program development. serial ports the adsp-217x incorporates two complete synchronous serial ports (sport0 and sport1) for serial communications and multiprocessor communication. here is a brief list of the capabilities of the adsp-217x sports. refer to the adsp-2100 family users manual for further details. sports are bidirectional and have a separate, double- buffered transmit and receive section. sports can use an external serial clock or generate their own serial clock internally. sports have independent framing for the receive and trans- mit sections. sections run in a frameless mode or with frame synchronization signals internally or externally generated. frame sync signals are active high or inverted, with either of two pulse widths and timings. sports support serial data word lengths from 3 to 16 bits and provide optional a-law and m -law companding according to ccitt recommendation g.711. sport receive and transmit sections can generate unique interrupts on completing a data word transfer. sports can receive and transmit an entire circular buffer of data with only one overhead cycle per data word. an interrupt is generated after a data buffer transfer. sport0 has a multichannel interface to selectively receive and transmit a 24 or 32 word, time-division multiplexed, serial bitstream. sport1 can be configured to have two external interrupts (irq0 and irq1) and the flag in and flag out signals. the internally generated serial clock may still be used in this configuration.
rev. a C4C ADSP-2171/adsp-2172/adsp-2173 pin description the adsp-217x is available in 128-lead tqfp and 128-lead pqfp packages. table i contains the pin descriptions. table i. adsp-217x pin list pin # group of input/ name pins output function address 14 o address output for program, data and boot memory spaces data 24 i/o data i/o pins for program and data memories. input only for boot memory space, with two msbs used as boot space addresses. reset 1 i processor reset input irq2 1 i external interrupt request #2 br 1 i external bus request input bg 1 o external bus grant output bgh 1 o external bus grant hang output pms 1 o external program memory select dms 1 o external data memory select bms 1 o boot memory select rd 1 o external memory read enable wr 1 o external memory write enable mmap 1 i memory map select clkin, xtal 2 i external clock or quartz crystal input clkout 1 o processor clock output hsel 1 i hip select input hack 1 o hip acknowledge output hsize 1 8/16 bit host select input 0 = 16-bit; 1 = 8-bit bmode 1 i boot mode select input 0 = eprom/data bus; 1 = hip hmd0 1 i bus strobe select input 0 = rd, wr; 1 = rw, ds hmd1 1 i hip address/data mode select input 0 = separate; 1 = multiplexed hrd /hrw 1 i hip read strobe/read/write select input hwr / hds 1 i hip write strobe/host data strobe select input hd15C0/ had15-0 16 i/o hip data/data and address ha2/ale 1 i host address 2/address latch enable input ha1C0/ unused 2 i host addresses 1 and 0 inputs sport0 5 i/o serial port 0 i/o pins (tfs0, rfs0, dt0, dr0, sclk0) sport1 5 i/o serial port 1 i/o pins or irq1 (tfs1) 1 i external interrupt request #1 irq0 (rfs1) 1 i external interrupt request #0 sclk1 1 o programmable clock output fo (dt1) 1 o flag output pin fi (dr1) 1 i flag input pin fl2C0 3 o general purpose flag output pins v dd 6 power supply pins gnd 11 ground pins pwd 1 i powerdown pin pwdack 1 o powerdown acknowledge pin host interface port the adsp-217x host interface port is a parallel i/o port that al- lows for an easy connection to a host processor. through the hip, the adsp-217x can be used as a memory-mapped periph- eral to a host computer. the hip can be thought of as an area of dual-ported memory, or mailbox registers, that allow commu- nication between the computational core of the adsp-217x and the host computer. the hip is completely asynchronous. the host processor can write data into the hip while the adsp-217x is operating at full speed. the hip can be configured with the following pins: hsize configures hip for 8-bit or 16-bit communication with the host processor. bmode (when mmap = 0) determines whether the adsp- 217x boots from the host processor (through the hip) or ex- ternal eprom (through the data bus). hmd0 configures the bus strobes as separate read and write strobes, or a single read/write select and a host data strobe. hmd1 selects separate address (3-bit) and data (16-bit) buses, or a multiplexed, 16-bit address/data bus with address latch enable. tying these pins to appropriate values configures the adsp- 217x for straight-wire interface to a variety of industry-standard microprocessors and microcomputers. in 8-bit reads, the adsp-217x three-states the upper eight bits of the bus. when the host processor writes an 8-bit value to the hip, the upper eight bits are all zeros. for additional informa- tion refer to the adsp-2100 family users manual . hip operation the hip contains six data registers (hdr5C0) and two status registers (hsr7C6) with an associated hmask register for masking interrupts from individual hip data registers. all hip data registers are memory-mapped into the internal data memory of the adsp-217x. hip transfers can be managed us- ing either interrupts or a polling scheme. these registers are shown in the section adsp-217x registers. the hip allows a software reset to be performed by the host processor. the internal software reset signal is asserted for five adsp-217x processor cycles.
ADSP-2171/adsp-2172/adsp-2173 rev. a C5C interrupts the interrupt controller allows the processor to respond to the eleven possible interrupts and reset with minimum overhead. the adsp-217x provides up to three external interrupt input pins, irq0 , irq1 and irq2 . irq2 is always available as a dedi- cated pin; sport1 may be reconfigured for irq0 , irq1 , and the flags. the adsp-217x also supports internal interrupts from the timer, the host interface port, the two serial ports, software, and the powerdown control circuit. the interrupt levels are in- ternally prioritized and individually maskable (except power- down and reset). the input pins can be programmed to be either level- or edge-sensitive. the priorities and vector ad- dresses of all interrupts are shown in table ii, and the interrupt registers are shown in figure 2. interrupts can be masked or unmasked with the imask regis- ter. individual interrupt requests are logically anded with the bits in imask; the highest priority unmasked interrupt is then selected.the powerdown interrupt is nonmaskable. the adsp-217x masks all interrupts for one instruction cycle following the execution of an instruction that modifies the imask register. this does not affect autobuffering. the interrupt control register, icntl, allows the external in- terrupts to be either edge- or level-sensitive. interrupt routines can either be nested with higher priority interrupts taking prece- dence or processed sequentially. the ifc register is a write-only register used to force and clear interrupts generated from software. table ii. interrupt priority & interrupt vector addresses interrupt vector source of interrupt address (hex) reset (or power-up with pucr = 1) 0000 ( highest priority ) powerdown (nonmaskable) 002c irq2 0004 hip write 0008 hip read 000c sport0 transmit 0010 sport0 receive 0014 software interrupt 1 0018 software interrupt 0 001c sport1 transmit or irq1 0020 sport1 receive or irq0 0024 timer 0028 ( lowest priority ) on-chip stacks preserve the processor status and are automati- cally maintained during interrupt handling. the stacks are twelve levels deep to allow interrupt nesting. the following instructions allow global enable or disable servic- ing of the interrupts (including powerdown), regardless of the state of imask. disabling the interrupts does not affect autobuffering. ena ints; dis ints; when you reset the processor, the interrupt servicing is enabled. figure 2. interrupt registers timer sport1 receive or irq0 sport1 transmit or irq1 software 0 software 1 sport0 receive sport0 transmit irq2 irq2 sport0 transmit sport0 receive software 1 software 0 sport1 transmit or irq1 sport1 receive or irq0 timer interrupt force interrupt clear ifc 9876543210 10 11 12 13 14 15 0 0 0 0 0 0 0 0 0 0 0 0 0 000 irq0 sensitivity irq1 sensitivity irq2 sensitivity interrupt nesting 1 = enable, 0 = disable 0 icntl 1 = edge 0 = level 43210 10 11 12 13 14 15 9876543210 irq2 hip write hip read sport0 transmit sport0 receive imask 1 = enable, 0 = disable 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 timer irq0 or sport1 receive irq1 or sport1 transmit software 0 software 1
rev. a C6C ADSP-2171/adsp-2172/adsp-2173 low power operation the adsp-217x has three low power modes that significantly reduce the power dissipation when the device operates under standby conditions. these modes are: powerdown idle slow idle the clkout pin may also be disabled to reduce external power dissipation. the clkout pin is controlled by bit 14 of sport0 autobuffer control register, dm[0x3ff3]. powerdown the adsp-217x processor has a low power feature that lets the processor enter a very low power dormant state through hard- ware or software control. here is a brief list of powerdown fea- tures. refer to the adsp-2100 family users manual , chapter 9 system interface for detailed information about the powerdown feature. powerdown mode holds the processor in cmos standby with a maximum current of less than 100 m a in some modes. quick recovery from powerdown. the processor begins ex- ecuting instructions in as few as 100 clkin cycles. support for an externally generated ttl or cmos processor clock. the external clock can continue running during powerdown without affecting the lowest power rating and 100 clkin cycle recovery. support for crystal operation includes disabling the oscillator to save power (the processor automatically waits 4096 clkin cycles for the crystal oscillator to start and stabilize), and let- ting the oscillator run to allow 100 clkin cycle startup. powerdown is initiated by either the powerdown pin ( pwd ) or the software powerdown force bit. interrupt support allows an unlimited number of instructions to be executed before optionally powering down. the powerdown interrupt also can be used as a non-maskable, edge sensitive interrupt. context clear/save control allows the processor to continue where it left off or start with a clean context when leaving the powerdown state. the reset pin also can be used to terminate powerdown, and the host software reset feature can be used to terminate powerdown under certain conditions. powerdown acknowledge pin indicates when the processor has entered powerdown. idle when the adsp-217x is in the idle mode, the processor waits indefinitely in a low power state until an interrupt occurs. when an unmasked interrupt occurs, it is serviced; execution then continues with the instruction following the idle instruction. slow idle the idle instruction is enhanced on the adsp-217x to let the processors internal clock signal be slowed during idle , further reducing power consumption. the reduced clock frequency, a programmable fraction of the normal clock rate, is specified by a selectable divisor given in the idle instruction. the format of the instruction is idle (n); where n = 16, 32, 64, or 128. this instruction keeps the proces- sor fully functional, but operating at the slower clock rate. while it is in this state, the processors other internal clock signals, such as sclk, clkout, and timer clock, are reduced by the same ratio. the default form of the instruction, when no clock divisor is given, is the standard idle instruction. when the idle (n) instruction is used, it effectively slows down the processors internal clock and thus its response time to in- coming interruptsCCthe 1-cycle response time of the standard idle state is increased by n , the clock divisor. when an enabled interrupt is received, the adsp-217x will remain in the idle state for up to a maximum of n processor cycles ( n = 16, 32, 64, or 128) before resuming normal operation. when the idle (n) instruction is used in systems that have an externally generated serial clock (sclk), the serial clock rate may be faster than the processors reduced internal clock rate. under these conditions, interrupts must not be generated at a faster rate than can be serviced, due to the additional time the processor takes to come out of the idle state (a maximum of n processor cycles). system interface figure 3 shows a basic system configuration with the adsp- 217x, two serial devices, a host processor, a boot eprom, and optional external program and data memories. up to 14k words of data memory and 16k words of program memory can be sup- ported. programmable wait state generation allows the processor to interface easily to slow memories. the adsp-217x also pro- vides one external interrupt and two serial ports or three exter- nal interrupts and one serial port. clock signals the adsp-217x can be clocked by either a crystal or by a ttl- compatible clock signal. the clkin input cannot be halted, changed during operation, or operated below the specified frequency during normal opera- tion. the only exception is while the processor is in the power- down state. for additional information, refer to chapter 9, adsp-2100 family users manual for detailed information on this powerdown feature. if an external clock is used, it should be a ttl-compatible sig- nal running at half the instruction rate. the signal is connected to the processors clkin input. when an external clock is used, the xtal input must be left unconnected. the adsp-217x uses an input clock with a frequency equal to half the instruction rate; a 16.67 mhz input clock yields a 30 ns processor cycle (which is equivalent to 33 mhz). normally, in- structions are executed in a single processor cycle. all device timing is relative to the internal instruction clock rate, which is indicated by the clkout signal when enabled.
ADSP-2171/adsp-2172/adsp-2173 rev. a C7C figure 3. adsp-217x basic system configuration because the adsp-217x includes an on-chip oscillator circuit, an external crystal may be used. the crystal should be con- nected across the clkin and xtal pins, with two capacitors connected as shown in figure 4. a parallel-resonant, fundamen- tal frequency, microprocessor-grade crystal should be used. clkin clkout xtal adsp-217x figure 4. external crystal connections a clock output (clkout) signal is generated by the processor at the processors cycle rate. this can be enabled and disabled by the clkodis bit in the sport0 autobuffer control reg- ister, dm[0x3ff3]. reset the reset signal initiates a master reset of the adsp-217x. the reset signal must be asserted during the power-up se- quence to assure proper initialization. reset during initial power-up must be held long enough to allow the internal clock sclk rfs tfs dt dr adsp-217x clkin clkout v dd serial port 0 gnd serial port 1 data address pms dms bms rd wr 14 24 16 8 24 serial device 14 2 xtal mmap bg br irq2 reset sclk rfs or irq0 tfs or irq1 dt or fo dr or fi ad cs data memory & peripherals a d cs oe we program memory (optional) note: the two msbs of the data bus are used as the msbs of the boot eprom address. this is only required for the 27c256 and 27c512. a d boot memory serial device (optional) (optional) d 15-8 e.g., eprom 27c64 27c128 27c256 27c512 host mode fl2-0 4 6 97 16 host processor (optional) 3 hip control hip hip data/addr pwdack pwd clock or crystal d 23-22 d 23-8 oe we oe cs (optional) to stabilize. if reset is activated any time after power-up, the clock continues to run and does not require stabilization time. the power-up sequence is defined as the total time required for the crystal oscillator circuit to stabilize after a valid v dd is ap- plied to the processor, and for the internal phase-locked loop (pll) to lock onto the specific crystal frequency. a minimum of 2000 clkin cycles ensures that the pll has locked but does not include the crystal oscillator start-up time. during this power-up sequence the reset signal should be held low. on any subsequent resets, the reset signal must meet the mini- mum pulse width specification, t rsp . the reset input contains some hysteresis; however, if you use an rc circuit to generate your reset signal, the use of an ex- ternal schmidt trigger is recommended. the master reset sets all internal stack pointers to the empty stack condition, masks all interrupts and clears the mstat reg- ister. when reset is released, if there is no pending bus re- quest and the chip is configured for booting (mmap = 0), the boot-loading sequence is performed. then the first instruction is fetched from internal program memory location 0x0000.
rev. a C8C ADSP-2171/adsp-2172/adsp-2173 program memory interface the on-chip program memory address bus (pma) and the on- chip program memory data bus (pmd) are multiplexed with on-chip dma and dmd buses, creating a single external data bus and a single external address bus. the 14-bit address bus directly addresses up to 16k words. 10k words of memory for adsp-217x with optional 8k rom and 2k words of memory for the non-rom version are on-chip. the data bus is bidirec- tional and 24 bits wide to external program memory. program memory may contain code and data. the program memory data lines are bidirectional. the program memory select ( pms ) signal indicates access to the program memory and can be used as a chip select signal. the write ( wr ) signal indicates a write operation and is used as a write strobe. the read ( rd ) signal indicates a read operation and is used as a read strobe or output enable signal. the adsp-217x writes data from its 16-bit registers to the 24- bit program memory using the px register to provide the lower eight bits. when it reads data (not instructions) from 24-bit pro- gram memory to a 16-bit data register, the lower eight bits are placed in the px register. program memory maps adsp-217x program memory can be mapped in two ways, depending on the state of the mmap pin. figure 5 shows the different configura- tions. when mmap = 0, internal ram occupies 2k words be- ginning at address 0x0000. in this configuration, the boot loading sequence (described in boot memory interface) is au- tomatically initiated when reset is released. 37ff 3800 3fff 0000 mmap = 1 bmode = 0 2k external 27ff 2800 8k internal rom (romenable = 1) or 4k external 2k internal ram 07ff 0800 8k external (romenable = 0) 2k internal ram not booted 6k external 3fff 0000 27ff 2800 07ff 0800 mmap = 1 bmode = 1 8k internal rom (romenable defaults to 1 during reset) mmap = 0 bmode = 0 or 1 2k internal ram booted 6k external 3fff 0000 27ff 2800 07ff 0800 or 8k external (romenable = 0) 8k internal rom (romenable = 1) figure 5. adsp-217x memory maps when mmap = 1, words of external program memory begin at address 0x0000 and internal ram is located in the upper 2k words, beginning at address 0x3800. in this configuration, pro- gram memory is not loaded although it can be written to and read from under program control. the optional rom always resides at locations pm[0x0800] through pm[0x27ff] regardless of the state of the mmap pin. the rom is enabled by setting the romenable bit in the data memory wait state control register, dm[0x3ffe]. when the romenable bit is set to 1, addressing program memory in this range will access the on-chip rom. when set to zero, addressing program memory in this range will access external program memory. the romenable bit is set to 0 on chip re- set unless mmap and bmode = 1. the program memory interface can generate 0 to 7 wait states for external memory devices; default is to 7 wait states after reset . boot memory interface the adsp-217x can load on-chip memory from external boot memory space. the boot memory space consists of 64k by 8-bit space, divided into eight separate 8k by 8-bit pages. three bits in the system control register select which page is loaded by the boot memory interface. another bit in the system control regis- ter allows the user to force a boot loading sequence under soft- ware control. boot loading from page 0 after reset is initiated automatically if mmap = 0. the boot memory interface can generate 0 to 7 wait states; it defaults to 7 wait states after reset . this allows the adsp- 217x to boot from a single low cost eprom such as a 27c256. program memory is booted one byte at a time and converted to 24-bit program memory words. the bms and rd signals are used to select and to strobe the boot memory interface. only 8-bit data is read over the data bus, on pins d8Cd15. to accommodate addressing up to eight pages of boot memory, the two msbs of the data bus are used in the boot memory interface as the two msbs of the boot space address. the adsp-2100 family assembler and linker support the cre- ation of programs and data structures requiring multiple boot pages during execution. rd and wr must always be qualified by pms , dms , or bms to ensure the correct program, data, or boot memory accessing. hip booting the adsp-217x can also boot programs through its host inter- face port. if bmode = 1 and mmap = 0, the adsp-217x boots from the hip. if bmode = 0, the adsp-217x boots through the data bus (in the same way as the adsp-2101), as described above in boot memory interface. for additional in- formation about hip booting, refer to the adsp-2100 family users manual , chapter 7, host interface port. the adsp-2100 family development software includes a util- ity program called the hip splitter. this utility allows the cre- ation of programs that can be booted via the adsp-217xs hip, in a similar fashion as eprom-bootable programs generated by the prom splitter utility.
ADSP-2171/adsp-2172/adsp-2173 rev. a C9C stand-alone rom execution when the mmap and bmode pins both are set to 1, the rom is automatically enabled and execution commences from program memory location 0x0800 at the start of rom. this feature lets an embedded design operate without external memory components. to operate in this mode, the rom coded program must copy an interrupt vector table to the appropriate locations in program memory ram. in this mode, the rom enable bit defaults to 1 during reset. table iii. boot summary table bmode = 0 bmode = 1 mmap = 0 boot from eprom, boot from hip, then then execution starts execution starts at at internal ram internal ram location location 0x0000 0x0000 mmap = 1 no booting, execution stand-alone mode, starts at external memory execution starts at location 0x0000 internal rom location 0x0800 ordering procedure for adsp-2172 processors to place an order for a custom rom-coded adsp-2172 pro- cessor, you must: 1. complete the following forms contained in the adsp rom ordering package , available from your analog devices sales representative: adsp-2172 rom specification form rom release agreement rom nre agreement & minimum quantity order (mqo) acceptance agreement for pre-production rom products. 2. return the forms to analog devices along with two copies of the memory image file (.exe file) of your rom code. the files must be supplied on two 3.5" or 5.25" floppy disks for ibm pc (dos 2.01 or higher). 3. place a purchase order with analog devices for nonrecurring engineering charges (nre) associated with rom product development. after this information is received, it is entered into analog devices rom manager system which assigns a custom rom model number to the product. this model number will be branded on all prototype and production units manufactured to these specifications. to minimize the risk of code being altered during this process, analog devices verifies that the .exe files on both floppy disks are identical, and recalculates the checksums for the .exe file en- tered into the rom manager system. the checksum data, in the form of a rom memory map, a hard copy of the .exe file, and a rom data verification form are returned to you for ins pection. a signed rom verification form and a purchase order for pro- duction units are required prior to any product being manufac- tured. prototype units may be applied toward the minimum order quantity. upon completion of the prototype manufacture, analog devices will ship prototype units and a delivery schedule update for pro- duction units. an invoice against your purchase order for the nre charges is issued at this time. there is a charge for each rom mask generated and a mini- mum order quantity. consult your sales representative for details. a separate order must be placed for parts of a specific package type, temperature range, and speed grade. data memory interface the data memory address (dma) bus is 14 bits wide. the bidi- rectional external data bus is 24 bits wide, with the upper 16 bits (d8Cd23) used for data memory data (dmd) transfers. the data memory select ( dms ) signal indicates access to the data memory and can be used as a chip select signal. the write ( wr ) signal indicates a write operation and can be used as a write strobe. the read ( rd ) signal indicates a read operation and can be used as a read strobe or output enable signal. the adsp-217x supports memory-mapped i/o, with the pe- ripherals memory mapped into the data or program memory ad- dress spaces and accessed by the processor in the same manner. data memory map the on-chip data memory ram resides in the 2k words of data memory beginning at address 0x3000, as shown in figure 6. in addition, data memory locations from 0x3800 to the end of data memory at 0x3fff are reserved. control registers for the sys- tem, timer, wait state configuration, host interface port, and se- rial port operations are located in this region of memory. 3bff 3c00 37ff 3800 data memory 12k external 3fff 0000 2fff 3000 1k reserved memory mapped registers/ reserved 2k internal data ram 03ff 0400 07ff 0800 wait states dwait 2 (10k external) 3fff 0000 2fff 3000 no wait states dwait 0 (1k external) dwait 1 (1k external) figure 6. adsp-217x data memory map the remaining 12k of data memory is external. external data memory is divided into three zones, each associated with its own wait state generator. by mapping peripherals into different zones, you can accommodate peripherals with different wait state requirements. all zones default to 7 wait states after reset . for compatibility with other adsp-2100 family pro- cessors, bit definitions for dwait 3 and dwait4 are shown in the data memory wait state control register, but they are not used by the adsp-217x.
rev. a C10C ADSP-2171/adsp-2172/adsp-2173 bus request & bus grant the adsp-217x can relinquish control of the data and address buses to an external device. when the external device requires access to memory, it asserts the bus request ( br ) signal. if the adsp-217x is not performing an external memory access, then it responds to the active br input in the following processor cycle by: three-stating the data and address buses and the pms , dms , bms , rd , wr output drivers, asserting the bus grant ( bg ) signal, and halting program execution. if the go mode is enabled, the adsp-217x will not halt pro- gram execution until it encounters an instruction that requires an external memory access. if the adsp-217x is performing an external memory access when the external device asserts the br signal, then it will not three-state the memory interfaces or assert the bg signal until the processor cycle after the access completes, which can be up to eight cycles later depending on the number of wait states. the instruction does not need to be completed when the bus is granted. if a single instruction requires two external memory ac- cesses, the bus will be granted between the two accesses. when the br signal is released, the processor releases the bg signal, reenables the output drivers and continues program ex- ecution from the point where it stopped. the bus request feature operates at all times, including when the processor is booting and when reset is active. the new bus grant hang logic and associated bgh pin allow the adsp-217x to operate in a multiprocessor environment with a minimal number of wasted processor cycles. the bus grant hang pin is asserted when the adsp-217x desires a cycle, but cannot execute it because the bus is granted to some other processor. with the bgh signal, the other processor(s) in the system can be alerted that the adsp-217x is hung and release the bus by deasserting bus request. once the bus is released the adsp-217x executes the external access and deasserts bgh . this is a signal to the other processors that external memory is now available. adsp-217x registers figure 7 summarizes all the registers in the adsp-217x. some registers store values. for example, ax0 stores an alu oper- and; i4 stores a dag2 pointer. other registers consist of control bits and fields, or status flags. for example, astat contains status flags from arithmetic operations, and fields in dwait control the numbers of wait states for different zones of data memory. a secondary set of registers in all computational units allows a single-cycle context switch. the bit and field definitions for control and status registers are given in the rest of this section, except for imask, icntl and ifc, which are defined earlier in this data sheet. the system control register, dwait register, timer registers, hip control registers, hip data registers, and sport control registers are all mapped into data memory; that is, registers are accessed by reading and writing data memory locations rather than register names. the particular data memory address is shown with each memory-mapped register. register bit values shown on the following pages are the default bit values after reset. if no values are shown, the bits are indeter- minate at reset. reserved bits are shown in gray; these bits should always be written with zeros. mac mr0 mr1 mf mr2 mx0 mx1 my0 my1 dma bus pma bus dmd bus pmd bus 14 powerdown control logic program rom 8k x 24 program sram 2k x 24 dag 2 m4 m5 m6 m7 l4 l5 l6 l7 i4 i5 i6 i7 dag 1 m0 m1 m2 m3 l0 l1 l2 l3 i0 i1 i2 i3 program sequencer count stack 4 x 14 cntr owrcntr status stack 12 x 25 imask mstat astat sstat icntl ifc pc stack 16 x 14 loop stack 4 x 18 dm wait control system control 0x3fff 0x3ffe host interface port data status hmask 0x3fe0-0x3fe5 0x3fe6-0x3fe7 0x3fe8 alu af ar ax0 ay1 ay0 ax1 shifter sr0 sr1 si se sb sport 1 control registers 0x3ff2-0x3fef rx1 tx1 sport 0 control registers 0x3ffa-0x3ff3 rx0 tx0 px timer tperiod tcount tscale 0x3ffd 0x3ffc 0x3ffb flags 14 16 24 data sram 2k x 16 figure 7. adsp-217x registers control register
ADSP-2171/adsp-2172/adsp-2173 rev. a C11C control registers sstat (read-only) pc stack empty pc stack overflow count stack empty count stack overflow status stack empty status stack overflow loop stack empty loop stack overflow 76543210 1 0 1 0 1 0 1 0 data register bank select 0 = primary, 1 = secondary bit reverse mode enable (dag1) alu overflow latch mode enable ar saturation mode enable mac result placement 0 = fractional, 1 = integer timer enable go mode enable mstat 6543210 0 0 0 0 0 0 0 system control register 0x3fff pwait program memory wait states 1514131211109876543210 bpage boot page select bwait boot wait states bforce boot force bit sport0 enable 1 = enabled, 0 = disabled sport1 enable 1 = enabled, 0 = disabled sport1 configure 1 = serial port 0 = fi, fo, irq0, irq1, sclk 1 0 1 0 0 0 0 01 11 1 1 0 0 0 0x3ffc timer registers 0x3ffd 0x3ffb 1514131211109876543210 tperiod period register tcount counter register tscale scaling register 0 0 0 0 0 0 00 az alu result zero an alu result negative av alu overflow ac alu carry as alu x input sign aq alu quotient mv mac overflow ss shifter input sign 76543210 astat 0 0 0 0 0 0 0 0
rev. a C12C ADSP-2171/adsp-2172/adsp-2173 control registers rom enable/data memory wait state control register 0x3ffe dwait4 dwait0 dwait1 dwait2 dwait3 rom enable 1 = enable 0 = disable 1 1 1 1 1 1 1 01 11 1 1 1 1 1 1514131211109876543210 sport0 control register 0x3ff6 multichannel enable mce internal serial clock generation isclk receive frame sync required rfsr receive frame sync width rfsw multichannel frame delay mfd only if multichannel mode enabled transmit frame sync required tfsr transmit frame sync width tfsw slen serial word length dtype data format 00 = right justify, zero-fill unused msbs 01 = right justify, sign extend into unused msbs 10 = compand using m -law 11 = compand using a-law invrfs invert receive frame sync invtfs invert transmit frame sync (or invtdv invert transmit data valid only if multichannel mode enabled) irfs internal receive frame sync enable 0 0 0 0 0 0 0 00 00 0 0 0 0 0 1514131211109876543210 itfs internal transmit frame sync enable (or mcl multichannel length; 1 = 32 words, 0 = 24 words only if multichannel mode enabled) sport0 multichannel receive word enable registers 1 = channel enabled 0 = channel ignored sport0 multichannel transmit word enable registers 1 = channel enabled 0 = channel ignored 0x3ff9 1514131211109876543210 0x3ffa 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0x3ff7 1514131211109876543210 0x3ff8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADSP-2171/adsp-2172/adsp-2173 rev. a C13C control registers sport0 sclkdiv serial clock divide modulus 0x3ff5 sport0 rfsdiv receive frame sync divide modulus 0x3ff4 1514131211109876543210 1514131211109876543210 sport0 autobuffer control register 0x3ff3 1514131211109876543210 0 0 0 000 rbuf receive autobuffering enable tbuf transmit autobuffering enable rmreg receive autobuffer m register rireg receive autobuffer i register clkodis clkout disable control bit biasrnd mac biased rounding control bit tireg transmit autobuffer i register tmreg transmit autobuffer m register sport1 control register 0x3ff2 flag out (read only) internal serial clock generation isclk receive frame sync required rfsr receive frame sync width rfsw transmit frame sync required tfsr transmit frame sync width tfsw slen serial word length dtype data format 00 = right justify, zero-fill unused msbs 01 = right justify, sign extend into unused msbs 10 = compand using m -law 11 = compand using a-law invrfs invert receive frame sync invtfs invert transmit frame sync irfs internal receive frame sync enable itfs internal transmit frame sync enable 1514131211109876543210 0 0 0 0 0 0 00 00 0 0 0 0 0
rev. a C14C ADSP-2171/adsp-2172/adsp-2173 control registers sport1 rfsdiv receive frame sync divide modulus 0x3ff0 1514131211109876543210 sport1 autobuffer control register 0x3fef 1514131211109876543210 0 0 0 000 rbuf receive autobuffer enable tbuf transmit autobuffer enable rmreg receive m register rireg receive i register tmreg transmit m register tireg transmit i register xtaldis xtal pin drive disable during powerdown 1 = disabled, 0 = enabled (disable xtal pin when no external crystal connected) xtaldelay 4096 cycle delay enable 1 = delay, 0 = no delay pdforce powerdown force pucr powerup context reset enable 1 = soft reset (context clear), 0 = resume execution sport1 sclkdiv serial clock divide modulus 0x3ff1 1514131211109876543210 hip data registers hdr5 hdr4 hdr3 hdr2 hdr1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 hdr0 0x3fe4 0x3fe3 0x3fe2 0x3fe1 0x3fe0 0x3fe5 hmask register host hdr5 read host hdr4 read host hdr3 read host hdr2 read host hdr1 read host hdr0 read host hdr0 write host hdr1 write host hdr2 write host hdr3 write host hdr4 write host hdr5 write 1514131211109876543210 0 0 0 0 0 0 00 00 0 0 0 0 0 0 interrupt enables 1 = enable 0 = disable 0x3fe8
ADSP-2171/adsp-2172/adsp-2173 rev. a C15C control registers instruction set description the adsp-217x assembly language instruction set has an alge- braic syntax that was designed for ease of coding and read- ability. the assembly language, which takes full advantage of the processors unique architecture, offers the following benefits: the algebraic syntax eliminates the need to remember cryptic assembler mnemonics. for example, a typical arithmetic add instruction, such as ar = ax0 + ay0, resembles a simple equation. every instruction assembles into a single, 24-bit word that can execute in a single instruction cycle. the syntax is a superset adsp-2100 family assembly lan- guage and is completely source and object code compatible with other family members. programs may need to be relo- cated to utilize internal memory and conform to the adsp- 217xs interrupt vector and reset vector map. sixteen condition codes are available. for conditional jump, call, return, or arithmetic instructions, the condition can be checked and the operation executed in the same instruction cycle. multifunction instructions allow parallel execution of an arith- metic instruction with up to two fetches or one write to pro- cessor memory space during a single instruction cycle. consult the adsp-2100 family users manual for a complete description of the syntax and an instruction set reference. biased rounding a new mode allows biased rounding in addition to the normal unbiased rounding. when the biasrnd bit is set to 0, the nor- mal unbiased rounding operations occur. when the biasrnd bit is set to 1, biased rounding occurs instead of the normal un- biased rounding. when operating in biased rounding mode all rounding operations with mr0 set to 0x8000 will round up, rather than only rounding odd mr1 values up. for example: mr value before rnd biased rnd result unbiased rnd result 00-0000-8000 00-0001-8000 00-0000-8000 00-0001-8000 00-0002-8000 00-0002-8000 00-0000-8001 00-0001-8001 00-0001-8001 00-0001-8001 00-0002-8001 00-0002-8001 00-0000-7fff 00-0000-7fff 00-0000-7fff 00-0001-7fff 00-0001-7fff 00-0001-7fff this mode only has an effect when the mr0 register contains 0x8000, all other rounding operation work normally. this mode was added to allow more efficient implementation of bit speci- fied algorithms which specify biased rounding such as the gsm speech compression routines. unbiased rounding is preferred for most algorithms. note: biasrnd bit is bit 12 of the sport0 autobuffer control register. hsr6 1514131211109876543210 0 0 0 0 0 0 0 00 00 0 0 0 0 0 host hdr0 write host hdr1 write host hdr2 write host hdr3 write host hdr4 write host hdr5 write 2171 hdr5 write 2171 hdr4 write 2171 hdr3 write 2171 hdr2 write 2171 hdr1 write 2171 hdr0 write overwrite mode software reset hsr7 1514131211109876543210 0 0 0 0 0 0 0 00 00 0 0 0 0 1 2171 hdr0 write 2171 hdr1 write 2171 hdr2 write 2171 hdr3 write 2171 hdr4 write 2171 hdr5 write 0x3fe6 0x3fe7
rev. a C16C ADSP-2171/adsp-2172/adsp-2173 example code the following example is a code fragment that performs the filter tap update for an adaptive (least-mean-squared algorithm) filter. notice that the computations in the instructions are written like algebraic equations. mf=mx0*my1 (rnd), mx0=dm (i2,m1); /* mf=error*beta */ mr=mx0*mf (rnd), ay0=pm (i6,ms); do adapt until ce; ar=mr1 + ay0, mx0=dm (i2,m1), ay0=pm (i6,m7); adapt: pm(i6,m6) =ar, mr=mx0*mf (rnd); modify (i2, m3); /* point to oldest data */ modify (i6, m7); /* point to start of data */ interrupt enable the adsp-217x supports an interrupt enable instruction. inter- rupts are enabled by default at reset. the instruction source code is specified as follows: syntax: ena ints; description: executing the ena ints instruction allows all unmasked interrupts to be serviced again. interrupt disable the adsp-217x supports an interrupt disable instruction. the instruction source code is specified as follows: syntax: dis ints; description: reset enables interrupt servicing. executing the dis ints instruction causes all interrupts to be masked without changing the contents of the imask register. disabling interrupts does not affect the autobuffer circuitry, which will operate normally whether or not interrupts are enabled. the disable interrupt instruction masks all user interrupts including the powerdown interrupt.
ADSP-2171/adsp-2172Cspecifications recommended operating conditions k grade b grade parameter min max min max unit v dd supply voltage 4.5 5.5 4.5 5.5 v t amb ambient operating temperature 0 +70 C40 +85 c electrical characteristics k/b grades parameter test conditions min max unit v ih hi-level input voltage 1, 2 @ v dd = max 2.0 v v ih hi-level clkin voltage @ v dd = max 2.2 v v ih hi-level reset voltage @ v dd = max 2.2 v v il lo-level input voltage 1, 3 @ v dd = min 0.8 v v oh hi-level output voltage 1, 4, 5 @ v dd = min i oh = C0.5 ma 2.4 v @ v dd = min i oh = C100 m a 6 v dd C 0.3 v v ol lo-level output voltage 1, 4, 5 @ v dd = min i ol = 2 ma 0.4 v i ih hi-level input current 3 @ v dd = max v in = v dd max 10 m a i il lo-level input current 3 @ v dd = max v in = 0 v 10 m a i ozh tristate leakage current 7 @ v dd = max, v in = v dd max 8 10 m a i ozl tristate leakage current 7 @ v dd = max, v in = 0 v 8 10 m a i dd supply current (idle) 9, 10 @ v dd = max 18 ma i dd supply current (dynamic) 10 @ v dd = max t ck = 30 ns 11 75 ma i dd supply current (powerdown) 10 lowest power mode 12 100 m a c i input pin capacitance 3, 6, 13 @ v in = 2.5 v, f in = 1.0 mhz, t amb = 25 c8pf c o output pin capacitance 6, 7, 13, 14 @ v in = 2.5 v, f in = 1.0 mhz, t amb = 25 c8pf notes 1 bidirectional pins: d0-d23, rfs0, rfs1, sclk0, sclk1, tfs0, tfs1, hd0-hd15/had0-had15. 2 input only pins: reset , irq2 , br , mmap, dr0, dr1, hsel , hsize, bmode, hmd0, hmd1, hrd /hwr, hwr / hds , pwd , ha2/ale, ha1-0. 3 input only pins: clkin, reset , irq2 , br , mmap, dr0, dr1, hsel , hsize, bmode, hmd0, hmd1, hrd /hwr, hwr / hds , pwd , ha2/ale, ha1-0. 4 output pins: bg , pms , dms , bms , rd , wr , pwdack, a0-a13, dt0, dt1, clkout, hack , fl2-0, bgh . 5 although specified for ttl outputs, all ADSP-2171/adsp-2172 outputs are cmos-compatible and will drive to v dd and gnd, assuming no dc loads. 6 guaranteed but not tested. 7 three-statable pins: a0-a13, d0-d23, pms , dms , bms , rd , wr , dt0, dt1, sclk0, sclk1, tfs0, tfs1, rfs0, rsf1, hd0-hd15/had0-had15. 8 0 v on br, clkin active (to force three-state condition). 9 idle refers to ADSP-2171/adsp-2172 state of operation during execution of idle instruction. deasserted pins are driven to either v dd or gnd. current reflects device operation with clkout disabled. 10 current reflects device operating with no output loads. 11 v in = 0.4 v and 2.4 v. for typical figures for supply currents, refer to power dissipation section. 12 see chapter 9, of the adsp-2100 family users manual for details. 13 applies to tqfp and pqfp package types. 14 output pin capacitance is the capacitive load for any three-state output pin. specifications subject to change without notice. ADSP-2171/adsp-2172/adsp-2173 C17C rev. a
rev. a C18C ADSP-2171/adsp-2172/adsp-2173 ADSP-2171/adsp-2172 memory requirements this chart links common memory device specification names and ADSP-2171/adsp-2172 timing parameters for your convenience. common parameter memory device name function specification name t asw a0-a13, dms , pms address setup to setup before wr low write start t aw a0-a13, dms , pms setup address setup before wr deasserted to write end t wra a0-a13, dms , pms address hold time hold after wr deasserted t dw data setup before wr high data setup time t dh data hold after wr high data hold time t rdd rd low to data valid oe to data valid t aa a0-a13, dms , pms , address access time bms to data valid ADSP-2171/adsp-2172 absolute maximum ratings * supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v input voltage . . . . . . . . . . . . . . . . . . . . . C0.3 v to v dd + 0.3 v output voltage swing . . . . . . . . . . . . . . C0.3 v to v dd + 0.3 v operating temperature range (ambient) . . . . C40 c to +85 c storage temperature range . . . . . . . . . . . . . C65 c to +150 c lead temperature (5 sec) tqfp . . . . . . . . . . . . . . . . +280 c lead temperature (5 sec) pqfp . . . . . . . . . . . . . . . . . +280 c * stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd sensitivity the adsp-217x is an esd (electrostatic discharge) sensitive device. electrostatic charges readily accumulate on the human body and equipment and can discharge without detection. permanent damage may occur to devices subjected to high energy electrostatic discharges. the adsp-217x features proprietary esd protection circuitry to dissipate high energy discharges (human body model). per method 3015 of mil-std-883, the adsp-217x has been classified as a class 1 device. proper esd precautions are recommended to avoid performance degradation or loss of function- ality. unused devices must be stored in conductive foam or shunts, and the foam should be discharged to the destination before devices are removed. warning! esd sensitive device general notes use the exact timing information given. do not attempt to de- rive parameters from the addition or subtraction of others. while addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. consequently, you cannot meaningfully add up parameters to derive longer times. timing notes switching characteristics specify how the processor changes its signals. you have no control over this timing; it is dependent on the internal design. timing requirements apply to signals that are controlled outside the processor, such as the data input for a read operation. timing requirements guarantee that the processor operates cor- rectly with another device. switching characteristics tell you what the device will do under a given circumstance. also, use the switching characteristics to ensure any timing requirement of a device connected to the processor (such as memory) is satisfied. ADSP-2171/adsp-2172 timing parameters
ADSP-2171/adsp-2172/adsp-2173 rev. a C19C ADSP-2171/adsp-2172 parameter min max unit clock signals t ck is defined as 0.5 t cki. the ADSP-2171/adsp-2172 uses an input clock with a frequency equal to half the instruction rate; a clock (which is equivalent to 60 ns) yields a 30 ns processor cycle 16.67 mhz input (equivalent to 33 mhz). t ck values within the range of 0.5 t cki period should be substituted for all relevant timing parameters to obtain specification value. example: t ckh = 0.5t ck C 7 ns = 0.5 (30 ns) C 7 ns = 8 ns. timing requirement: t cki clkin period 60 150 ns t ckil clkin width low 20 ns t ckih clkin width high 20 ns switching characteristic: t ckl clkout width low 0.5t ck C 7 ns t ckh clkout width high 0.5t ck C 7 ns t ckoh clkin high to clkout high 0 20 ns control signals timing requirement: t rsp reset width low 5t ck 1 ns note 1 applies after power-up sequence is complete. internal phase lock loop requires no more than 2000 clkin cycles assuming stable clkin (not including crystal oscillator start-up time). clkin clkout t ckil t ckoh t ckh t ckl t cki t ckih figure 8. clock signals
rev. a C20C ADSP-2171/adsp-2172/adsp-2173 ADSP-2171/adsp-2172 parameter min max unit interrupts and flags timing requirement: t ifs irqx or fi setup before clkout low 1, 2, 3 0.25t ck + 15 ns t ifh irqx or fi hold after clkout high 1, 2, 3 0.25t ck ns switching characteristic: t foh flag output hold after clkout low 4 0.5t ck C 7 ns t fod flag output delay from clkout low 4 0.5t ck + 5 ns notes 1 if irqx and fi inputs meet t ifs and t ifh setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on the following cycle. (refer to interrupt controller operation in the program control chapter of the users manual for further information on interrupt servicing.) 2 edge-sensitive interrupts require pulse widths greater than 10 ns; level-sensitive interrupts must be held low until serviced. 3 irqx = irq0 , irq1 , and irq2 . 4 flag output = fl0, fl1, fl2, and fo. clkout flag outputs irq x fi t ifs t fod t foh t ifh figure 9. interrupts and flags
ADSP-2171/adsp-2172/adsp-2173 rev. a C21C ADSP-2171/adsp-2172 parameter min max unit bus request/grant timing requirement: t bh br hold after clkout high 1 0.25t ck + 2 ns t bs br setup before clkout low 1 0.25t ck + 17 ns switching characteristic: t sd clkout high to dms , pms , bms , 0.25t ck + 16 ns rd , wr disable t sdb dms , pms , bms , rd , wr disable to bg low 0 ns t se bg high to dms , pms , bms , rd , wr enable 0 ns t sec dms , pms , bms , rd , wr enable to clkout high 0.25t ck C 7 ns t sdbh dms , pms , bms , rd , wr disable to bgh low 2 0ns t seh bgh high to dms , pms , bms , rd , wr enable 2 0ns notes 1 br is an asynchronous signal. if br meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on the following cycle. refer to the adsp-2100 family users manual for br / bg cycle relationships. 2 bgh is asserted when the bus is granted and the processor requires control of the bus to continue. t bs br t bh clkout pms , dms bms , rd wr bg clkout t sd t sdb t se t sec t sdbh bg h t seh figure 10. bus requestCbus grant
rev. a C22C ADSP-2171/adsp-2172/adsp-2173 ADSP-2171/adsp-2172 parameter min max unit memory read timing requirement: t rdd rd low to data valid 0.5t ck C 9 + w ns t aa a0Ca13, pms , dms , bms to data valid 0.75t ck C 10.5 + w ns t rdh data hold from rd high 0 ns switching characteristic: t rp rd pulse width 0.5t ck C 5 + w ns t crd clkout high to rd low 0.25t ck C 5 0.25t ck + 7 ns t asr a0Ca13, pms , dms , bms setup before rd low 0.25t ck C 6 ns t rda a0Ca13, pms , dms , bms hold after rd deasserted 0.25t ck C 3 ns t rwr rd high to rd or wr low 0.5t ck C 5 ns w = wait states x t ck . clkout a0?13 d t rda rd wr dms, pms bms t rwr t rp t asr t crd t rdd t aa t rdh figure 11. memory read
ADSP-2171/adsp-2172/adsp-2173 rev. a C23C ADSP-2171/adsp-2172 parameter min max unit memory write switching characteristic: t dw data setup before wr high 0.5 t ck C 7 + w ns t dh data hold after wr high 0.25t ck C 2 ns t wp wr pulse width 0.5t ck C 5 + w ns t wde wr low to data enabled 0 ns t asw a0Ca13, dms , pms setup before wr low 0.25t ck C 6 ns t ddr data disable before wr or rd low 0.25t ck C 7 ns t cwr clkout high to wr low 0.25t ck C 5 0.25 t ck + 7 ns t aw a0Ca13, dms , pms , setup before wr deasserted 0.75t ck C 9 + w ns t wra a0Ca13, dms , pms hold after wr deasserted 0.25t ck C 3 ns t wwr wr high to rd or wr low 0.5t ck C 5 ns w = wait states x t ck . clkout a0?13 d t wra wr dms, pms t wwr t wp t as w t aw t cwr rd t dh t dd r t wde t dw figure 12. memory write
rev. a C24C ADSP-2171/adsp-2172/adsp-2173 ADSP-2171/adsp-2172 parameter min max unit serial ports timing requirement: t sck sclk period 50 ns t scs dr/tfs/rfs setup before sclk low 4 ns t sch dr/tfs/rfs hold after sclk low 7 ns t scp sclk in width 20 ns switching characteristic: t cc clkout high to sclk out 0.25t ck 0.25t ck + 10 ns t scde sclk high to dt enable 0 ns t scdv sclk high to dt valid 15 ns t rh tfs/rfs out hold after sclk high 0 ns t rd tfs/rfs out delay from sclk high 15 ns t scdh dt hold after sclk high 0 ns t tde tfs(alt) to dt enable 0 ns t tdv tfs(alt) to dt valid 15 ns t scdd sclk high to dt disable 15 ns t rdv rfs (multichannel, frame delay zero) to dt valid 15 ns clkout sclk tfs rfs dr rfs in tfs in dt alternate frame mode t cc t cc t sck t scp t scp t scs t sch t rd t rh rfs out tfs out t scdv t scde t scdh t scdd t tde t tdv t rdv multichannel mode, frame delay 0 (mfd = 0) figure 13. serial ports
ADSP-2171/adsp-2172/adsp-2173 rev. a C25C ADSP-2171/adsp-2172 parameter min max unit host interface port separate data and address (hmd1 = 0) read strobe and write strobe (hmd0 = 0) timing requirement: t hsu ha2C0 setup before start of write or read 1, 2 5ns t hdsu data setup before end of write 3 5ns t hwdh data hold after end of write 3 3ns t hh ha2C0 hold after end of write or read 3, 4 3ns t hrwp read or write pulse width 5 20 ns switching characteristic: t hshk hack low after start of write or read 1, 2 015ns t hkh hack hold after end of write or read 3, 4 015ns t hde data enabled after start of read 2 0ns t hdd data valid after start of read 2 18 ns t hrdh data hold after end of read 4 0ns t hrdd data disabled after end of read 4 7ns notes 1 start of write = hwr low and hsel low. 2 start of read = hrd low and hsel low. 3 end of write = hwr high or hsel high. 4 end of read = hrd high or hsel high. 5 read pulse width = hrd low and hsel low, write pulse width = hwr low and hsel low. data hd15? hsel hwr hack ha2? address t hsu t hh t hwdh t hrwp t hshk t hkh t hdsu data hd15? hsel h rd hack ha2? address t hsu t hh t hrwp t hrdh t hkh t hshk t hrdd t hde t hdd figure 14. host interface port (hmd1 = 0, hmd0 = 0) host write cycle host read cycle
rev. a C26C ADSP-2171/adsp-2172/adsp-2173 ADSP-2171/adsp-2172 parameter min max unit host interface port separate data and address (hmd1 = 0) read strobe and write strobe (hmd0 = 1) timing requirement: t hsu ha2C0, hrw setup before start of write or read 1 5ns t hdsu data setup before end of write 2 5ns t hwdh data hold after end of write 2 3ns t hh ha2C0, hrw hold after end of write or read 2 3ns t hrwp read or write pulse width 3 20 ns switching characteristic: t hshk hack low after start of write or read 1 015ns t hkh hack hold after end of write or read 2 015ns t hde data enabled after start of read 1 0ns t hdd data valid after start of read 1 18 ns t hrdh data hold after end of read 2 0ns t hrdd data disabled after end of read 2 7ns notes 1 start of write or read = hds low and hsel low. 2 end of write or read = hds high and hsel high. 3 read or write pulse width = hds low and hsel low. data hd15? hsel hrw hack ha2? address t hsu t hh t hwdh t hrwp t hshk t hkh t hdsu h ds data hd15? hsel h ds hack ha2? address t hsu t hh t hrwp t hrdh t hkh t hshk t hde t hdd hrw t hrdd figure 15. host interface port (hmd1 = 0, hmd0 = 1) host write cycle host read cycle
ADSP-2171/adsp-2172/adsp-2173 rev. a C27C ADSP-2171/adsp-2172 parameter min max unit host interface port multiplexed data and address (hmd1 = 1) read strobe and write strobe (hmd0 = 0) timing requirement: t halp ale pulse width 10 ns t hasu had15C0 address setup, before ale low 5 ns t hah had15C0 address hold after ale low 2 ns t hals start of write or read after ale low 1, 2 10 ns t hdsu had15C0 data setup before end of write 3 5ns t hwdh had15C0 data hold after end of write 3 3ns t hrwp read or write pulse width 4 20 ns switching characteristic: t hshk hack low after start of write or read 1, 2 015ns t hkh hack hold after end of write or read 3, 5 015ns t hde had15C0 data enabled after start of read 2 0ns t hdd had15C0 data valid after start of read 2 18 ns t hrdh had15C0 data hold after end of read 0 ns t hrdd had15C0 data disabled after end of read 5 7ns notes 1 start of write = hwr low and hsel low. 2 start of read = hrd low and hsel low. 3 end of write = hwr high or hsel high. 4 read pulse width = hrd low and hsel low, write pulse width = hwr low and hsel low. 5 end of read = hrd high or hsel high. address t hdsu data hack hwr hsel hd15? t hrwp t hshk ale t halp t hals t hkh t hah t hasu t hwdh t hrdh t hrdd t hde address data hack hrd hsel had15? t hrwp t hshk ale t halp t hals t hkh t hah t hasu t hdd figure 16. host interface port (hmd1 = 1, hmd0 = 0) host write cycle host read cycle
rev. a C28C ADSP-2171/adsp-2172/adsp-2173 ADSP-2171/adsp-2172 parameter min max unit host interface port multiplexed data and address (hmd1 = 1) read strobe and write strobe (hmd0 = 1) timing requirement: t halp ale pulse width 10 ns t hasu had15C0 address setup before ale low 5 ns t hah had15C0 address hold after ale low 2 ns t hals start of write or read after ale low 1 10 ns t hsu hrw setup before start of write or read 1 5ns t hdsu had15C0 data setup before end of write 2 5ns t hwdh had15C0 data hold after end of write 2 3ns t hh hrw hold after end of write or read 2 3ns t hrwp read or write pulse width 3 20 ns switching characteristic: t hshk hack low after start of write or read 1 015ns t hkh hack hold after end of write or read 2 015ns t hde had15C0 data enabled after start of read 1 0ns t hdd had15C0 data valid after start of read 1 18 ns t hrdh had15C0 data hold after end of read 2 0ns t hrdd had15C0 data disabled after end of read 2 7ns notes 1 start of write or read = hds low and hsel low. 2 end of write or read = hds high and hsel high. 3 read or write pulse width = hds low and hsel low. address t hdsu data hack hrw hsel hd15? t hrwp t hshk ale t halp t hals t hkh t hah t hasu t hwdh hds t hh t hsu address data hack hrw hsel hd15? t hrwp t hshk ale t halp t hals t hkh t hah t hasu t hrdh hds t hh t hsu t hde t hdd t hrdd figure 17. host interface port (hmd1 = 1, hmd0 = 1) host write cycle host read cycle
ADSP-2171/adsp-2172/adsp-2173 rev. a C29C ADSP-2171/adsp-2172 environmental conditions ambient temperature rating: t amb = t case C (pd q ca ) t case = case temperature in c pd = power dissipation in w q ca = thermal resistance (case-to-ambient) q ja = thermal resistance (junction-to-ambient) q jc = thermal resistance (junction-to-case) package q ja q jc q ca tqfp 50 c/w 2 c/w 48 c/w pqfp 41 c/w 10 c/w 31 c/w power dissipation to determine total power dissipation in a specific application, the following equation should be applied for each output: c v dd 2 f c = load capacitance, f = output switching frequency. example: in an application where external data memory is used and no other outputs are active, power dissipation is calculated as follows: assumptions: ? external data memory is accessed every cycle with 50% of the address pins switching. ? external data memory writes occur every other cycle with 50% of the data pins switching. ? each address and data pin has a 10 pf total load at the pin. ? the application operates at v dd = 5.0 v and t ck = 30 ns. total power dissipation = p int + (c v dd 2 f ) p int = internal power dissipation from power vs. frequency graph (figure 18). ( c v dd 2 f ) is calculated for each output: # of pins c v dd 2 f address, dms 8 10 pf 5 2 v 33.3 mhz = 66.6 mw data output, wr 9 10 pf 5 2 v 16.67 mhz = 37.5 mw rd 1 10 pf 5 2 v 16.67 mhz = 4.2 mw clkout 1 10 pf 5 2 v 33.3 mhz = 8.3 mw 116.6 mw total power dissipation for this example is p int + 116.6 mw. valid for all temperature grades. 1 power reflects device operating with no output loads. 2 idle refers to ADSP-2171 state of operation during execution of idle instruction. deasserted pins are driven to either v dd or gnd. power reflects device operating with clkout disabled. 3 typical power dissipation at 5.0v v dd during execution of idle n instruction (clock frequency reduction). power reflects device operating with clkout disabled. power, internal v dd = 4.5v 186mw 382mw 229mw 148mw 110mw 27 23 21 19 17 15 25 13 31 29 33 v dd = 5.0v v dd = 5.5v 225 175 200 300 250 275 325 375 350 400 150 125 301mw power (p int ) ?mw 1 / t ck ?mhz power (p idle ) ?mw power, idle 50 40 45 65 55 60 70 80 75 85 35 30 27 23 21 19 17 15 25 13 31 29 33 1 / t ck ?mhz 48mw 37mw 26mw 82mw 48mw 64mw v dd = 4.5v v dd = 5.0v v dd = 5.5v idle; idle (16) idle (128) 27 23 21 19 17 15 25 13 31 29 33 1 / t ck ?mhz power (p idle n ) ?mw power, idle n modes 82mw 20mw 37mw 23mw 31mw 64mw 44 36 40 56 48 52 60 68 64 72 32 28 24 20 16 28mw 3 1, 2 1 figure 18. power vs. frequency
rev. a C30C ADSP-2171/adsp-2172/adsp-2173 ADSP-2171/adsp-2172 capacitive loading figures 19 and 20 show the capacitive loading characteristics of the ADSP-2171/adsp-2172. rise time (0.4v - 2.4v) ?ns 28 12 4 8 24 16 20 25 150 125 100 75 50 c l ?pf v dd = 4.5v figure 19. typical output rise time vs. load capacitance, c l (at maximum ambient operating temperature) +14 +4 ? +2 +12 +8 +10 25 150 125 100 75 50 c l ?pf nominal valid output delay or hold ?ns figure 20. typical output valid delay or hold vs. load capacitance, c l (at maximum ambient operating temperature) test conditions output disable time output pins are considered to be disabled when they have stopped driving and started a transition from the measured out- put high or low voltage to a high impedance state. the output disable time (t dis ) is the difference of t measured and t decay , as shown in the output enable/disable diagram. the time is the interval from when a reference signal reaches a high or low volt- age level to when the output voltages have changed by 0.5 v from the measured output high or low voltage. the decay time, t decay , is dependent on the capacitative load, c l , and the cur- rent load, i l , on the output pin. it can be approximated by the following equation: t decay = c l 0.5 v i l from which t dis = t measured t decay is calculated. if multiple pins (such as the data bus) are dis- abled, the measurement value is that of the last pin to stop driving. 3.0v 1.5v 0.0v 2.0v 1.5v 0.3v input output figure 21. voltage reference levels for ac measure- ments (except output enable/disable) output enable time output pins are considered to be enabled when that have made a transition from a high-impedance state to when they start driv- ing. the output enable time (t ena ) is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in the output enable/disable diagram. if multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving. 2.0v 1.0v t ena reference signal output t decay v oh (measured) output stops driving output starts driving t dis t measured v ol (measured) v oh (measured) ?0.5v v ol (measured) +0.5v high-impedance state. test conditions cause this voltage level to be approximately 1.5v. v oh (measured) v ol (measured) figure 22. output enable/disable to output pin 50pf +1.5v i oh i ol figure 23. equivalent device loading for ac measure- ments (including all fixtures)
adsp-2173Cspecifications recommended operating conditions k grade b grade parameter min max min max unit v dd supply voltage 3.0 3.6 3.0 3.6 v t amb ambient operating temperature 0 +70 C40 +85 c electrical characteristics k/b grades parameter test conditions min max unit v ih hi-level input voltage 1, 2 @ v dd = max 2.0 v v ih hi-level clkin voltage @ v dd = max 2.0 v v ih hi-level reset voltage @ v dd = max 2.2 v v il lo-level input voltage 1, 3 @ v dd = min 0.4 v v oh hi-level output voltage 1, 4, 5 @ v dd = min i oh = C0.5 ma 2.4 v @ v dd = min i oh = C100 ma 6 v dd C 0.3 v v ol lo-level output voltage 1, 4, 5 @ v dd = min i ol = 2 ma 0.4 v i ih hi-level input current 3 @ v dd = max v in = v dd max 10 m a i il lo-level input current 3 @ v dd = max v in = 0 v 10 m a i ozh tristate leakage current 7 @ v dd = max, v in = v dd max 8 10 m a i ozl tristate leakage current 7 @ v dd = max, v in = 0 v 8 10 m a i dd supply current (idle) 9, 10 @ v dd = max 7 ma i dd supply current (dynamic) 10 @ v dd = max t ck = 50 ns 11 27 ma i dd supply current (powerdown) 10 lowest power mode 12 100 m a c i input pin capacitance 3, 6, 13 @ v in = 2.5 v, f in = 1.0 mhz, t amb = 25 c8pf c o output pin capacitance 6, 7, 13, 14 @ v in = 2.5 v, f in = 1.0 mhz, t amb = 25 c8pf notes 1 bidirectional pins: d0-d23, rfs0, rfs1, sclk0, sclk1, tfs0, tfs1, hd0-hd15/had0-had15. 2 input only pins: reset , irq2 , br , mmap, dr0, dr1, hsel , hsize, bmode, hmd0, hmd1, hrd /hwr, hwr / hds , pwd , ha2/ale, ha1-0. 3 input only pins: clkin, reset , irq2 , br , mmap, dr0, dr1, hsel , hsize, bmode, hmd0, hmd1, hrd /hwr, hwr / hds , pwd , ha2/ale, ha1-0. 4 output pins: bg , pms , dms , bms , rd , wr , pwdack, a0-a13, dt0, dt1, clkout, hack , fl2-0, bgh . 5 although specified for ttl outputs, all adsp-2173 outputs are cmos-compatible and will drive to v dd and gnd, assuming no dc loads. 6 guaranteed but not tested. 7 three-statable pins: a0-a13, d0-d23, pms , dms , bms , rd , wr , dt0, dt1, sclk0, sclk1, tfs0, tfs1, rfs0, rsf1, hd0-hd15/had0-had15. 8 0 v on br, clkin active (to force three-state condition). 9 idle refers to adsp-2173 state of operation during execution of idle instruction. deasserted pins are driven to either v dd or gnd. current reflects device operation with clkout disabled. 10 current reflects device operating with no output loads. 11 v in = 0.4 v and 2.4 v. for typical figures for supply currents, refer to power dissipation section. 12 see chapter 9, of the adsp-2100 family users manual for details. 13 applies to tqfp and pqfp package types. 14 output pin capacitance is the capacitve load for any three-state output pin. specifications subject to change without notice. ADSP-2171/adsp-2172/adsp-2173 rev. a C31C
rev. a C32C ADSP-2171/adsp-2172/adsp-2173 adsp-2173 timing parameters general notes use the exact timing information given. do not attempt to de- rive parameters from the addition or subtraction of others. while addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. consequently, you cannot meaningfully add up parameters to derive longer times. timing notes switching characteristics specify how the processor changes its signals. you have no control over this timing; it is dependent on the internal design. timing requirements apply to signals that are controlled outside the processor, such as the data input for a read operation. timing requirements guarantee that the processor operates cor- rectly with another device. switching characteristics tell you what the device will do under a given circumstance. also, use the switching characteristics to ensure any timing requirement of a device connected to the processor (such as memory) is satisfied. memory requirements this chart links common memory device specification names and adsp-2173 timing parameters for your convenience. common parameter memory device name function specification name t asw a0-a13, dms , pms address setup to setup before wr low write start t aw a0-a13, dms , pms setup address setup before wr deasserted to write end t wra a0-a13, dms , pms address hold time hold after wr deasserted t dw data setup before wr high data setup time t dh data hold after wr high data hold time t rdd rd low to data valid oe to data valid t aa a0-a13, dms , pms , address access time bms to data valid
ADSP-2171/adsp-2172/adsp-2173 rev. a C33C adsp-2173 parameter min max unit clock signals t ck is defined as 0.5 t cki. the adsp-2173 uses an input clock with a frequency equal to half the instruction rate; a 10.0 mhz input clock (which is equivalent to 100 ns) yields a 50 ns processor cycle (equivalent to 20 mhz). t ck values within the range of 0.5 t cki period should be substituted for all relevant timing parameters to obtain specification value. example: t ckh = 0.5t ck C 10 ns = 0.5 (50 ns) C 10 ns = 15 ns. timing requirement: t cki clkin period 100 160 ns t ckil clkin width low 20 ns t ckih clkin width high 20 ns switching characteristic: t ckl clkout width low 0.5t ck C 10 ns t ckh clkout width high 0.5t ck C 10 ns t ckoh clkin high to clkout high 0 25 ns control signals timing requirement: t rsp reset width low 5t ck 1 ns note 1 applies after power-up sequence is complete. internal phase lock loop requires no more than 2000 clkin cycles assuming stable clkin (not including crystal oscillator start-up time). clkin clkout t ckil t ckoh t ckh t ckl t cki t ckih figure 24. clock signals
rev. a C34C ADSP-2171/adsp-2172/adsp-2173 adsp-2173 parameter min max unit interrupts and flags timing requirement: t ifs irqx or fi setup before clkout low 1, 2, 3 0.25t ck + 23 ns t ifh irqx or fi hold after clkout high 1, 2, 3 0.25t ck ns switching characteristic: t foh flag output hold after clkout low 4 0.5t ck C 10 ns t fod flag output delay from clkout low 4 0.5t ck + 5 ns notes 1 if irqx and fi inputs meet t ifs and t ifh setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on the following cycle. (refer to interrupt controller operation in the program control chapter of the users manual for further information on interrupt servicing.) 2 edge-sensitive interrupts require pulse widths greater than 10 ns; level-sensitive interrupts must be held low until serviced. 3 irqx = irq0 , irq1 , and irq2 . 4 flag output = fl0, fl1, fl2, and fo. clkout flag outputs irq x fi t ifs t fod t foh t ifh figure 25. interrupts and flags
ADSP-2171/adsp-2172/adsp-2173 rev. a C35C adsp-2173 parameter min max unit bus request/grant timing requirement: t bh br hold after clkout high 1 0.25t ck + 2 ns t bs br setup before clkout low 1 0.25t ck + 22 ns switching characteristic: t sd clkout high to dms , pms , bms , 0.25t ck + 16 ns rd , wr disable t sdb dms , pms , bms , rd , wr disable to bg low 0 ns t se bg high to dms , pms , bms , rd , wr enable 0 ns t sec dms , pms , bms , rd , wr enable to clkout high 0.25t ck C 10 ns t sdbh dms , pms , bms , rd , wr disable to bgh low 2 0ns t seh bgh high to dms , pms , bms , rd , wr enable 2 0ns notes 1 br is an asynchronous signal. if br meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on the following cycle. refer to the adsp-2100 family users manual for br / bg cycle relationships. 2 bgh is asserted when the bus is granted and the processor requires control of the bus to continue. t bs br t bh clkout pms , dms bms , rd wr bg clkout t sd t sdb t se t sec t sdbh bg h t seh figure 26. bus requestCbus grant
rev. a C36C ADSP-2171/adsp-2172/adsp-2173 adsp-2173 parameter min max unit memory read timing requirement: t rdd rd low to data valid 0.5t ck C 15 + w ns t aa a0Ca13, pms , dms , bms to data valid 0.75t ck C 20.5 + w ns t rdh data hold from rd high 0 ns switching characteristic: t rp rd pulse width 0.5t ck C 5 + w ns t crd clkout high to rd low 0.25t ck C 5 0.25t ck + 10 ns t asr a0Ca13, pms , dms , bms setup before rd low 0.25t ck C 7 ns t rda a0Ca13, pms , dms , bms hold after rd deasserted 0.25t ck C 3 ns t rwr rd high to rd or wr low 0.5t ck C 5 ns w = wait states x t ck . clkout a0?13 d t rda rd wr dms, pms bms t rwr t rp t asr t crd t rdd t aa t rdh figure 27. memory read
ADSP-2171/adsp-2172/adsp-2173 rev. a C37C adsp-2173 parameter min max unit memory write switching characteristic: t dw data setup before wr high 0.5 t ck C 7 + w ns t dh data hold after wr high 0.25t ck C 2 ns t wp wr pulse width 0.5t ck C 5 + w ns t wde wr low to data enabled 0 ns t asw a0Ca13, dms , pms setup before wr low 0.25t ck C 7 ns t ddr data disable before wr or rd low 0.25t ck C 7 ns t cwr clkout high to wr low 0.25t ck C 5 0.25 t ck + 10 ns t aw a0Ca13, dms , pms , setup before wr deasserted 0.75t ck C 11.5 + w ns t wra a0Ca13, dms , pms hold after wr deasserted 0.25t ck C 3 ns t wwr wr high to rd or wr low 0.5t ck C 5 ns w = wait states x t ck . clkout a0?13 d t wra wr dms, pms t wwr t wp t as w t aw t cwr rd t dh t dd r t wde t dw figure 28. memory write
rev. a C38C ADSP-2171/adsp-2172/adsp-2173 adsp-2173 parameter min max unit serial ports timing requirement: t sck sclk period 76.9 ns t scs dr/tfs/rfs setup before sclk low 8 ns t sch dr/tfs/rfs hold after sclk low 10 ns t scp sclk in width 28 ns switching characteristic: t cc clkout high to sclk out 0.25t ck 0.25t ck + 15 ns t scde sclk high to dt enable 0 ns t scdv sclk high to dt valid 20 ns t rh tfs/rfs out hold after sclk high 0 ns t rd tfs/rfs out delay from sclk high 20 ns t scdh dt hold after sclk high 0 ns t tde tfs(alt) to dt enable 0 ns t tdv tfs(alt) to dt valid 19 ns t scdd sclk high to dt disable 25 ns t rdv rfs (multichannel, frame delay zero) to dt valid 20 ns clkout sclk tfs rfs dr rfs in tfs in dt alternate frame mode t cc t cc t sck t scp t scp t scs t sch t rd t rh rfs out tfs out t scdv t scde t scdh t scdd t tde t tdv t rdv multichannel mode, frame delay 0 (mfd = 0) figure 29. serial ports
ADSP-2171/adsp-2172/adsp-2173 rev. a C39C adsp-2173 parameter min max unit host interface port separate data and address (hmd1 = 0) read strobe and write strobe (hmd0 = 0) timing requirement: t hsu ha2C0 setup before start of write or read 1, 2 8ns t hdsu data setup before end of write 3 8ns t hwdh data hold after end of write 3 3ns t hh ha2C0 hold after end of write or read 3, 4 3ns t hrwp read or write pulse width 5 30 ns switching characteristic: t hshk hack low after start of write or read 1, 2 020ns t hkh hack hold after end of write or read 3, 4 020ns t hde data enabled after start of read 2 0ns t hdd data valid after start of read 2 23 ns t hrdh data hold after end of read 4 0ns t hrdd data disabled after end of read 4 15 ns notes 1 start of write = hwr low and hsel low. 2 start of read = hrd low and hsel low. 3 end of write = hwr high or hsel high. 4 end of read = hrd high or hsel high. 5 read pulse width = hrd low and hsel low, write pulse width = hwr low and hsel low. data hd15? hsel hwr hack ha2? address t hsu t hh t hwdh t hrwp t hshk t hkh t hdsu data hd15? hsel h rd hack ha2? address t hsu t hh t hrwp t hrdh t hkh t hshk t hrdd t hde t hdd figure 30. host interface port (hmd1 = 0, hmd0 = 0) host write cycle host read cycle
rev. a C40C ADSP-2171/adsp-2172/adsp-2173 adsp-2173 parameter min max unit host interface port separate data and address (hmd1 = 0) read strobe and write strobe (hmd0 = 1) timing requirement: t hsu ha2C0, hrw setup before start of write or read 1 8ns t hdsu data setup before end of write 2 8ns t hwdh data hold after end of write 2 3ns t hh ha2C0, hrw hold after end of write or read 2 3ns t hrwp read or write pulse width 3 30 ns switching characteristic: t hshk hack low after start of write or read 1 020ns t hkh hack hold after end of write or read 2 020ns t hde data enabled after start of read 1 0ns t hdd data valid after start of read 1 23 ns t hrdh data hold after end of read 2 0ns t hrdd data disabled after end of read 2 15 ns notes 1 start of write or read = hds low and hsel low. 2 end of write or read = hds high and hsel high. 3 read or write pulse width = hds low and hsel low. data hd15? hsel hrw hack ha2? address t hsu t hh t hwdh t hrwp t hshk t hkh t hdsu h ds data hd15? hsel h ds hack ha2? address t hsu t hh t hrwp t hrdh t hkh t hshk t hde t hdd hrw t hrdd figure 31. host interface port (hmd1 = 0, hmd0 = 1) host write cycle host read cycle
ADSP-2171/adsp-2172/adsp-2173 rev. a C41C adsp-2173 parameter min max unit host interface port multiplexed data and address (hmd1 = 1) read strobe and write strobe (hmd0 = 0) timing requirement: t halp ale pulse width 15 ns t hasu had15C0 address setup, before ale low 5 ns t hah had15C0 address hold after ale low 2 ns t hals start of write or read after ale low 1, 2 15 ns t hdsu had15C0 data setup before end of write 3 8ns t hwdh had15C0 data hold after end of write 3 3ns t hrwp read or write pulse width 5 30 ns switching characteristic: t hshk hack low after start of write or read 1, 2 020ns t hkh hack hold after end of write or read 3, 4 020ns t hde had15C0 data enabled after start of read 2 0ns t hdd had15C0 data valid after start of read 2 23 ns t hrdh had15C0 data hold after end of read 0 ns t hrdd had15C0 data disabled after end of read 4 15 ns notes 1 start of write = hwr low and hsel low. 2 start of read = hrd low and hsel low. 3 end of write = hwr high or hsel high. 4 end of read = hrd high or hsel high. 5 read pulse width = hrd low and hsel low, write pulse width = hwr low and hsel low. address t hdsu data hack hwr hsel hd15? t hrwp t hshk ale t halp t hals t hkh t hah t hasu t hwdh t hrdh t hrdd t hde address data hack hrd hsel had15? t hrwp t hshk ale t halp t hals t hkh t hah t hasu t hdd figure 32. host interface port (hmd1 = 1, hmd0 = 0) host write cycle host read cycle
rev. a C42C ADSP-2171/adsp-2172/adsp-2173 adsp-2173 parameter min max unit host interface port multiplexed data and address (hmd1 = 1) read strobe and write strobe (hmd0 = 1) timing requirement: t halp ale pulse width 15 ns t hasu had15C0 address setup before ale low 5 ns t hah had15C0 address hold after ale low 2 ns t hals start of write or read after ale low 1 15 ns t hsu hrw setup before start of write or read 1 8ns t hdsu had15C0 data setup before end of write 2 8ns t hwdh had15C0 data hold after end of write 2 3ns t hh hrw hold after end of write or read 2 3ns t hrwp read or write pulse width 3 30 ns switching characteristic: t hshk hack low after start of write or read 1 020ns t hkh hack hold after end of write or read 2 020ns t hde had15C0 data enabled after start of read 1 0ns t hdd had15C0 data valid after start of read 1 23 ns t hrdh had15C0 data hold after end of read 2 0ns t hrdd had15C0 data disabled after end of read 2 15 ns notes 1 start of write or read = hds low and hsel low. 2 end of write or read = hds high and hsel high. 3 read or write pulse width = hds low and hsel low. address t hdsu data hack hrw hsel hd15? t hrwp t hshk ale t halp t hals t hkh t hah t hasu t hwdh hds t hh t hsu address data hack hrw hsel hd15? t hrwp t hshk ale t halp t hals t hkh t hah t hasu t hrdh hds t hh t hsu t hde t hdd t hrdd figure 33. host interface port (hmd1 = 1, hmd0 = 1) host write cycle host read cycle
ADSP-2171/adsp-2172/adsp-2173 rev. a C43C adsp-2173 environmental conditions ambient temperature rating: t amb = t case C (pd q ca ) t case = case temperature in c pd = power dissipation in w q ca = thermal resistance (case-to-ambient) q ja = thermal resistance (junction-to-ambient) q jc = thermal resistance (junction-to-case) package q ja q jc q ca tqfp 50 c/w 2 c/w 48 c/w pqfp 41 c/w 10 c/w 31 c/w power dissipation to determine total power dissipation in a specific application, the following equation should be applied for each output: c v dd 2 f c = load capacitance, f = output switching frequency. example: in an application where external data memory is used and no other outputs are active, power dissipation is calculated as follows: assumptions: ? external data memory is accessed every cycle with 50% of the address pins switching. ? external data memory writes occur every other cycle with 50% of the data pins switching. ? each address and data pin has a 10 pf total load at the pin. ? the application operates at v dd = 3.3 v and t ck = 50 ns. total power dissipation = p int + (c v dd 2 f ) p int = internal power dissipation from power vs. frequency graph (figure 18). ( c v dd 2 f ) is calculated for each output: # of pins c v dd 2 f address, dms 8 10 pf 3.3 2 v 20 mhz = 17.4 mw data output, wr 9 10 pf 3.3 2 v 10 mhz = 9.8 mw rd 1 10 pf 3.3 2 v 10 mhz = 1.1 mw clkout 1 10 pf 3.3 2 v 20 mhz = 2.2 mw 30.5 mw total power dissipation for this example is p int + 30.5 mw. 45 35 12 40 60 50 55 65 70 75 85 80 90 19 20 18 17 16 15 14 13 power, internal 1 power (p int ) ?mw 1 / t ck ?mhz 71 mw 57 mw 89 mw 55 mw 32 mw 44 mw 11 9 12 10 14 12 13 15 16 17 19 18 20 19 20 18 17 16 15 14 13 power (p idle ) ?mw power, idle 1, 2 1 / t ck ?mhz 16.2 mw 12.7 mw 20.5 mw 15.5 mw 8.5 mw 11.8 mw valid for all temperature grades. 1 power reflects device operating with no output loads. 2 idle refers to adsp-2173 state of operation during execution of idle instruction. deasserted pins are driven to either v dd or gnd. power reflects device operating with clkout disabled. 3 typical power dissipation at 3.3v v dd during execution of idle n instruction (clock frequency reduction). power reflects device operating with clkout disabled. power, idle n modes 3 7 5 12 6 10 8 9 11 12 13 15 14 16 19 20 18 17 16 15 14 13 idle; idle (16) idle (128) 1 / t ck ?mhz power (p idle n ) ?mw 7.8 mw 7.2 mw 16.2 mw 11.8 mw 6.2 mw 6.8 mw figure 34. power vs. frequency
rev. a C44C ADSP-2171/adsp-2172/adsp-2173 adsp-2173 capacitive loading figures 35 and 36 show the capacitive loading characteristics of the adsp-2173. 16 8 25 12 28 20 24 150 125 100 75 50 v dd = 3.3 v c l ?pf rise time (0.4 v ?2.4 v) ?ns figure 35. typical output rise time vs. load capacitance, c l (at maximum ambient operating temperature) nominal -2 25 +4 +2 +8 +10 +12 150 125 100 75 50 +14 valid output delay or hold ?ns c l ?pf figure 36. typical output valid delay or hold vs. load capacitance, c l (at maximum ambient operating temperature) test conditions output disable time output pins are considered to be disabled when they have stopped driving and started a transition from the measured out- put high or low voltage to a high impedance state. the output disable time (t dis ) is the difference of t measured and t decay , as shown in the output enable/disable diagram. the time is the interval from when a reference signal reaches a high or low volt- age level to when the output voltages have changed by 0.5 v from the measured output high or low voltage. the decay time, t decay , is dependent on the capacitative load, c l , and the cur- rent load, i l , on the output pin. it can be approximated by the following equation: t decay = c l 0.5 v i l from which t dis = t measured t decay is calculated. if multiple pins (such as the data bus) are dis- abled, the measurement value is that of the last pin to stop driving. input output v dd 2 v dd 2 figure 37. voltage reference levels for ac measure- ments (except output enable/disable) output enable time output pins are considered to be enabled when that have made a transition from a high-impedance state to when they start driv- ing. the output enable time (t ena ) is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in the output enable/disable diagram. if multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving. 2.0v 1.0v t ena reference signal output t decay v oh (measured) output stops driving output starts driving t dis t measured v ol (measured) v oh (measured) ?0.5v v ol (measured) +0.5v high-impedance state. test conditions cause this voltage level to be approximately 1.5v. v oh (measured) v ol (measured) figure 38. output enable/disable to output pin 50pf i oh i ol v dd 2 figure 39. equivalent device loading for ac measure- ments (including all fixtures)
ADSP-2171/adsp-2172/adsp-2173 rev. a C45C 128-lead tqfp package pinout 1 128 65 64 39 38 103 102 top view (pins down) hd10 hsize hd6 hd7 hd8 hd9 hd11 hd12 hd13 hd14 hd15 pwdack gnd gnd nc nc nc hwr/hds hrd /hrw wr rd bms dms pms dd v dd v nc bmode gnd nc dt0 tfs0 rfs0 dr0 sclk0 dr1/fi sclk1 fl0 fl1 fl2 nc nc hmd0 hmd1 hack irq2 reset rfs1/ irq0 dt1/fo tfs1/ irq1 v dd gnd gnd gnd ha2/ale ha1 ha0 hd5 hd4 hd3 hd2 hd1 hd0 gnd a0 a1 a2 a3 a4 a5 a6 a7 xtal clkin clkout gnd a8 a9 a10 a11 a12 a13 nc mmap nc nc hsel dd v dd v pwd nc nc d23 d22 d21 d20 d19 gnd d18 d17 d16 d15 d14 d13 d12 d11 gnd d10 d9 d8 d7 d6 d5 d4 d3 gnd d2 d1 d0 nc nc nc nc nc br bg v dd bgh nc = no connect
rev. a C46C ADSP-2171/adsp-2172/adsp-2173 tqfp pin configurations tqfp pin tqfp pin tqfp pin tqfp pin number name number name number name number name 1 gnd 33 a13 65 nc 97 d20 2 gnd 34 nc 66 bgh 98 d21 3 ha2/ale 35 mmap 67 nc 99 d22 4 ha1 36 nc 68 nc 100 d23 5 ha0 37 nc 69 nc 101 nc 6 hsel 38 pwd 70 br 102 nc 7 hd5 39 irq2 71 nc 103 nc 8 hd4 40 nc 72 bg 104 nc 9 hd3 41 bmode 73 d0 105 nc 10 hd2 42 nc 74 d1 106 rd 11 hd1 43 nc 75 d2 107 wr 12 hd0 44 v dd 76 gnd 108 gnd 13 v dd 45 gnd 77 d3 109 gnd 14 gnd 46 reset 78 d4 110 v dd 15 v dd 47 nc 79 d5 111 pms 16 a0 48 hack 80 d6 112 dms 17 a1 49 hmd0 81 d7 113 bms 18 a2 50 hmd1 82 d8 114 pwdack 19 a3 51 dt0 83 d9 115 hd15 20 a4 52 tfs0 84 d10 116 hd14 21 a5 53 rfs0 85 gnd 117 hd13 22 a6 54 dr0 86 v dd 118 hd12 23 a7 55 sclk0 87 d11 119 hd11 24 xtal 56 dt1/fo 88 d12 120 v dd 25 clkin 57 tfs1/ irq1 89 d13 121 hd10 26 clkout 58 rfs1/ irq0 90 d14 122 hd9 27 gnd 59 gnd 91 d15 123 hd8 28 a8 60 dr1/f1 92 d16 124 hd7 29 a9 61 sclk1 93 d17 125 hd6 30 a10 62 fl0 94 d18 126 hsize 31 a11 63 fl1 95 gnd 127 hrd /hrw 32 a12 64 fl2 96 d19 128 hwr / hds nc = these pins must remain unconnected.
ADSP-2171/adsp-2172/adsp-2173 rev. a C47C outline dimensions 128-lead metric thin plastic quad flatpack (tqfp) millimeters inches symbol min typ max min typ max a 1.60 0.063 a 1 0.05 0.15 0.002 0.006 a 2 1.30 1.40 1.50 0.051 0.055 0.059 d 15.75 16.00 16.25 0.620 0.630 0.640 d 1 13.90 14.00 14.10 0.547 0.551 0.555 d 3 12.50 12.58 0.492 0.495 e 21.75 22.00 22.25 0.856 0.866 0.876 e 1 19.90 20.00 20.10 0.783 0.787 0.792 e 3 18.50 18.58 0.728 0.731 l 0.45 0.60 0.75 0.018 0.024 0.030 e 0.42 0.50 0.58 0.017 0.019 0.023 b 0.17 0.22 0.27 0.007 0.009 0.011 0.10 0.004 d 1 128 103 102 65 64 39 38 e b d 1 d 3 d top view (pins down) e 3 e 1 e a l a 2 seating plane d a 1
rev. a C48C ADSP-2171/adsp-2172/adsp-2173 128-lead pqfp package pinout hrd /hrw 128l pqfp (28mm x 28mm) nc gnd gnd hwr / hds hsize hd6 hd7 hd8 hd9 hd10 gnd gnd wr nc rd nc nc nc nc hd11 hd12 hd13 hd14 hd15 pwdack bms dms pms nc dd v dd v 1 128 97 96 65 64 33 32 top view (pins down) ha2/ale ha1 ha0 hsel hd5 hd4 hd3 hd2 hd1 hd0 gnd a0 a1 a2 a3 a4 a5 a6 a7 xtal clkin clkout gnd a8 a9 a10 a11 a12 a13 nc dd v dd v d23 d22 d21 d20 d19 gnd d18 d17 d16 d15 d14 d13 d12 d11 gnd d10 d9 d8 d7 d6 d5 d4 d3 gnd d2 d1 d0 nc nc br bg dd v nc = no connect mmap nc pwd irq2 nc bmode nc nc gnd reset nc rfs1/ irq0 gnd dr1/fi nc sclk1 fl0 fl1 fl2 hack hmd0 hmd1 dt0 tfs0 rfs0 dr0 sclk0 dt1/fo tfs1/ irq1 nc bgh dd v
ADSP-2171/adsp-2172/adsp-2173 rev. a C49C pqfp pin configurations pqfp pin pqfp pin pqfp pin pqfp pin number name number name number name number name 1 ha2/ale 33 mmap 65 nc 97 nc 2 ha1 34 nc 66 br 98 nc 3 ha0 35 pwd 67 nc 99 nc 4 hsel 36 irq2 68 bg 100 nc 5 hd5 37 nc 69 d0 101 nc 6 hd4 38 bmode 70 d1 102 nc 7 hd3 39 nc 71 d2 103 rd 8 hd2 40 nc 72 gnd 104 wr 9 hd1 41 v dd 73 d3 105 gnd 10 hd0 42 gnd 74 d4 106 gnd 11 v dd 43 reset 75 d5 107 v dd 12 gnd 44 nc 76 d6 108 pms 13 v dd 45 hack 77 d7 109 dms 14 a0 46 hmd0 78 d8 110 bms 15 a1 47 hmd1 79 d9 111 pwdack 16 a2 48 dt0 80 d10 112 hd15 17 a3 49 tfs0 81 gnd 113 hd14 18 a4 50 rfs0 82 v dd 114 hd13 19 a5 51 dr0 83 d11 115 hd12 20 a6 52 sclk0 84 d12 116 hd11 21 a7 53 dt1/fo 85 d13 117 v dd 22 xtal 54 tfs1/ irq1 86 d14 118 hd10 23 clkin 55 rfs1/ irq0 87 d15 119 hd9 24 clkout 56 gnd 88 d16 120 hd8 25 gnd 57 dr1/f1 89 d17 121 hd7 26 a8 58 sclk1 90 d18 122 hd6 27 a9 59 fl0 91 gnd 123 hsize 28 a10 60 fl1 92 d19 124 hrd /hrw 29 a11 61 fl2 93 d20 125 hwr / hds 30 a12 62 nc 94 d21 126 gnd 31 a13 63 bgh 95 d22 127 gnd 32 nc 64 nc 96 d23 128 nc nc = these pins must remain unconnected.
rev. a C50C ADSP-2171/adsp-2172/adsp-2173 outline dimensions 128-lead metric thin plastic quad flatpack (pqfp) millimeters inches symbol min typ max min typ max a 4.07 0.160 a 1 0.25 0.010 a 2 3.17 3.49 3.67 0.125 0.137 0.144 d, e 30.95 31.20 31.45 1.219 1.228 1.238 d 1 , e 1 27.90 28.00 28.10 1.098 1.102 1.106 d 3 , e 3 24.73 24.80 24.87 0.974 0.976 0.979 l 0.65 0.88 1.03 0.031 0.035 0.041 e 0.73 0.80 0.87 0.029 0.031 0.034 b 0.30 0.35 0.45 0.012 0.014 0.018 0.10 0.004 d a l a 2 seating plane d a 1 1 128 97 96 65 64 33 32 e b d 1 d 3 d e 3 e 1 e top view (pins down)
ADSP-2171/adsp-2172/adsp-2173 rev. a C51C ordering guide* ambient instruction temperature rate package part number** range (mhz) description ADSP-2171kst-133 0 c to +70 c 33.33 128-lead tqfp ADSP-2171bst-133 C40 c to +85 c 33.33 128-lead tqfp ADSP-2171ks-133 0 c to +70 c 33.33 128-lead pqfp ADSP-2171bs-133 C40 c to +85 c 33.33 128-lead pqfp ADSP-2171kst-104 0 c to +70 c 26 128-lead tqfp ADSP-2171bst-104 C40 c to +85 c 26 128-lead tqfp ADSP-2171ks-104 0 c to +70 c 26 128-lead pqfp ADSP-2171bs-104 C40 c to +85 c 26 128-lead pqfp adsp-2173bst-80 C40 c to +85 c 20 128-lead tqfp adsp-2173bs-80 C40 c to +85 c 20 128 lead pqfp *refer to section titled ordering procedure for adsp-2172 rom processors for information about ordering rom-coded parts. **s = plastic quad flatpack, st = plastic thin quad flatpack.
printed in u.s.a. c1984aC6C11/95 C52C

▲Up To Search▲

Price & Availability of ADSP-2171

	To Download ADSP-2171 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .